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IRF9630S, SiHF9630S
Vishay Siliconix
Peak Dio d e Recovery d V/ d t Test Circuit
D.U.T.
Circuit layout con s ideration s
? Low stray inductance
? G round plane
? Low leakage inductance
current tran s former
-
+
R g
? dV/dt controlled by R g
? I S D controlled by duty factor “D”
? D.U.T. - device under te s t
+
-
V DD
Note
? Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
V GS = - 10 V a
D.U.T. l S D waveform
Rever s e
recovery
Body diode forward
current
Re-applied
D.U.T. V D S waveform
current
dI/dt
Diode recovery
dV/dt
V DD
voltage
Inductor current
Body diode forward drop
Ripple ≤ 5 %
I S D
Note
a. V GS = - 5 V for logic level and - 3 V drive device s
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91085 .
Document Number: 91085
S11-1051-Rev. C, 30-May-11
www.vishay.com
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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